At the present time, most chemical etching of copper on microelectronic substrates is performed with either copper or ferric chlorides, chromium salts, alkaline-ammonia, hydrogen peroxide-sulfuric acid or nitric acid compositions. Each of these compositions has certain limitations and disadvantages as described hereinbelow.
The metal etchants, in particular the chromium salts, create a deleterious environmental impact. It is also known that chromium salts are human carcinogens; therefore, their use and disposal are especially problematic.
Nitric acid, either alone or in combination with sulfuric acid or copper nitrate, has been reported by Battey (U.S. Pat. No. 4,695,348) to be useful for etching copper in circuit boards. However, nitrogous oxide gas is a byproduct of this process. Moreover, the process provides anisotropic etching only for certain orientations of copper (i.e., the top surface of the copper crystal structure must have a Miller index of (111) and (200) orientation). This requires first sputtering copper and then electrodepositing more copper. In lieu of sputtered copper, evaporative deposition or electroless deposition is also possible.
The alkaline-ammonia compositions are used commercially because they are relatively fast, have substantial copper-carrying capacity and are reasonably tolerant of some metal resists and some dry film resists. However, these same compositions have poor selectivity for copper versus other metals and alloys. Significant process control is required to achieve acceptable selectivity. It is also known that these compositions may not work well with fine line copper geometries. Furthermore, the dissolved copper is difficult to recover. Also, fumes from the ammonia composition present worker exposure concerns.
The hydrogen peroxide-sulfuric acid compositions used in copper etching processes are very clean to operate and can be recycled. However, these same compositions have relatively slow etching rates and require substantial cooling for stability control due to the autodecomposition reaction of the hydrogen peroxide. Additionally, both the performance of the process and the decomposition of the peroxide are very sensitive to trace impurities via homo- or hetero-catalysis. Stabilizers are necessary for peak performance but these are metal specific. Brasch (U.S. Pat. No. 4,378,270) teaches phenol-sulfonic acid for copper containing solutions. It is also known from Alderuccio, et al (U.S. Pat. No. 3,269,881) that these compositions are adversely affected by chloride or bromide ion at levels of 2 mg/liter, causing reduced etch rates. Elias (U.S. Pat. No. 4,130,455) teaches that the addition of sodium or potassium thiosulfate can counteract this effect.
But use of these additives does not address the basic problem of the catalytic decomposition of the peroxide discussed hereinabove. This decomposition has two important: implications: firstly, the depletion of the peroxide in the etchant solution reduces the etchant rate; and secondly, there is potential for uncontrolled decomposition of large volumes of high temperature solutions, generating high concentrations of oxygen and increasing the safety risks therefrom. Because decomposition of the peroxide is accelerated at elevated temperatures, processing temperatures must be kept low. This adversely affects the rate of the etching process and exacerbates the already low copper-carrying capacity of the peroxide-sulfuric acid composition. Finally, the process generates voluminous quantities of copper sulfate, which are difficult to reclaim or dispose of. It is possible to electroplate out the copper from the copper sulfate. Typically, however, this copper does not deposit as an adherent homogeneous ingot deposit, but rather comes out as a powder which sluffs off and makes recovery difficult. Brasch (U.S. Pat. No. 4,378,270) describes the use of phosphoric acid to assist in producing smooth adherent copper deposits on a cathodic surface, but this is at the expense of a slower etchant rate.
The prior art etchants are used in processes to manufacture various types of microelectronic packages such as printed circuit boards having planar resistors and laminate chip carriers. For each of these packages, complex processes must be employed to circumvent the above-mentioned problems.
There are several problems in attempting to etch fine line (less than 0.004" width) printed circuits when using classical processes and chemistry. These problems are defined as follows:
1) Fluid mechanics problems--With classical print and etch processes, a photoresist is applied to the printed circuit board. Dry film photoresist materials are generally available in thicknesses of 0.001" and greater, and typically are 0.0012" or greater. As etching progresses through the Cu, the trough defined by the photoresist and the etched Cu becomes progressively deeper and the depth to width aspect ratio becomes progressively greater. As the aspect ratio increases, the etch uniformity decreases due to the non-uniform nature of getting fresh etchant into this trough. One solution to this problem has been to use liquid resist materials that can be applied by spray or electrodeposition methods at a reduced thickness.
2) Galvanic etching--Many processors utilize a nickel/gold plated etch mask over the copper for etching. Due to the significant difference in electrode potentials between the Au and Cu metals, the copper is etched at an accelerated, almost uncontrollable rate in currently known chemistries, except possibly for ammoniacal etchants. Galvanic etch effects can be compensated for somewhat by increasing the width of the Ni/Au resist image, such that the etched Cu image after galvanic etch effects is of the desired width. The down side to this technique is that it is not compatible with fine line/fine space etch requirements. This galvanic etch effect may also result in an undesirable line geometry after etching. Another potential solution would be to eliminate the Au, using only Ni as the etch mask. This solution would require an etchant that does not etch Ni, but does etch Cu. Until now, such an etchant has been unknown, except for chrome-sulfuric chemistries, which have their own problems of environmental impacts, waste treatment, and poor copper capacity.
3) Miscellaneous Au etch mask problems--In addition to the galvanic etch problems, Au masking suffers from very high material costs, and inability to use for innerlayer etching due to the inability to subsequently adhere epoxy to Au during composite lamination of the innerlayers.
Subtractive etching to produce fine line circuits is especially difficult for external circuit layers on plated through-hole (PTH) printed circuit boards. Prior art technology has been unable to provide uniform line widths along with high-yielding processes. This problem is primarily due to the thick photoresist that must be used to tent PTHs on printed circuit boards. Furthermore, the thickness of the photoresist layer is related to the width of area to be etched; viz., the greater the thickness of the photoresist, the greater the spacing must be between the protected circuit lines. This relationship therefore limits the density of the circuit lines if thick photoresists are necessary.
To fabricate a photoresist circuit pattern, prior art methods initially apply a thin copper foil to a substrate and then subsequently apply, image and develop a photoresist to create a circuit pattern. The exposed, thin copper foil in the through-holes is electroless and/or electrolytically plated with copper followed by a nickel-gold etch mask. The photoresist is then stripped away and the underlying thin copper foil is fast-etched while the etch mask theoretically protects the newly formed circuit lines and through-holes. This process is very difficult to control because it requires electroplating thin patterns rather than full-panel plating. Furthermore, the etching process using either peroxide-sulfuric acid or alkaline-ammonia compositions induces galvanic etching between the nickel-gold and copper interface. This is the cause of undesirable circuit line cross-sections which, in turn, creates poor functional reliability.
The use of laminate chip carriers (LCCs) in electronic packaging is growing at an ever-increasing rate. The predominant use of LCCs is with wire bond chip attachment. The use of wire bond requires that circuits be fully encapsulated in nickel-gold or other noble metallurgy. Nickel-gold both provides a wire bondable surface and prevents copper migration shorts between circuit lines in the harsh operating environment of LCCs.
The preferred metallurgy for wire bonding is electrolytically-plated nickel-gold. Due to the dense central wiring used in LCCs, temporary commoning bars must be incorporated into the central wiring area. These temporary commoning bars are then removed from the circuit after nickel-gold plating has been performed. Prior art technology currently requires applying a new photoresist layer and etching the commoning bars through openings in the photoresist, typically with a cupric chloride etch solution. The photoresist is required in order to minimize galvanic etch undercutting when copper etching occurs in the presence of nickel-gold (or other noble metals) with the above-mentioned etchant compositions--especially cupric chloride.
Since the photoresist does not completely provide protection from galvanic etching, current practice is to intentionally create a reduced opening size to compensate for the galvanic etch effects.
It is also known that application and removal of photoresist materials to and from the nickel-gold plated features can have adverse effects on wire bond yield and reliability. Hence, for wire bond LCCs it would be desirable, for the reasons discussed above, as well as for cost considerations, to have a commoning bar etchant or process that would not require a photoresist application. This can be achieved only by identifying a process that does not cause galvanic etching effects. Elimination of the galvanic etch effect will most importantly provide a superior etch profile to the fabricated circuit lines, allowing for higher quality devices.
For etching of planar resistors, an etchant must be selective to copper relative to the nickel/phosphorus (NiP) underlayer; otherwise, precise control must be maintained on the etchant chemistry and etch-process parameters, such as etch endpoint. Chromic acid compositions had been the etchants of choice due to their complete selectivity to copper, but environmental concerns have essentially precluded their use. None of the other prior art etchant compositions, including alkaline ammonia, are sufficiently selective to fabricate precision resistors. Due to this lack of selectivity, even with tight processing controls, manufacturing variability of planar resistors are typically high.
With hydrogen peroxide-sulfuric acid or alkaline-ammonium etchant compositions, there is a tendency for the copper to be etched more quickly from areas where fine lines are present than from larger areas. This results in etch mask undercutting of the fine lines while the larger areas are being cleared of copper. Furthermore, neither process is truly anisotropic. U.S. Pat. Nos. 4,497,687 and 4,545,850, both issued to N. Nelson, describe the use of nitric acid and nitric acid with sulfuric acid regenerator, respectively, to produce an anisotropic etch. But it is reported that in some instances this defect still occurs.
Etch masks can be made from various materials including plastics, ink, photoresists or a metal such as gold, solder, or a nickel-tin alloy. The mask serves the purpose of protecting the underlying material. In the case of microelectronic devices, the underlying material is typically copper. Common masks used in the prior art were solder or tin-nickel alloys. These masks effectively protected the underlying copper strata; but due to environmental concerns, they have essentially been eliminated from use. Noble metals and their alloys have alleviated the environmental problems associated with the heavy metal masks. However, in the process of etching copper using these masks, undercutting of the copper can occur at the interface of the noble metal surface and the copper surface, as described hereinabove, causing galvanic etching.
It can therefore be seen that although the process of etching copper in microelectronic packages has been performed for a lengthy period of time, many unresolved problems are still associated with the process. Some of these problems create limitations on designs of these microelectronic packages. Considering that requirements for higher circuit density, faster speed and greater reliability of these devices are constantly becoming more stringent, it is clearly understood that reduced complexity of manufacture and improved etchant performance are still required.
An etchant chemistry and associated process has now been invented to overcome all of these problems, and be able to etch fine line circuits. This etchant is not prone to the galvanic etch effects caused by Au masking, and further, does not etch Ni.
The present invention therefore provides for an etching composition useful in printed circuit board fabrication having the following independent advantages:
a) has high selectivity for copper; PA1 b) eliminates undercutting due to galvanic etching; PA1 c) has high copper carrying capacity; PA1 d) remains stable during its use; PA1 e) has wide process latitude; PA1 f) has high etchant rates at room temperatures; PA1 g) is environmentally acceptable; and PA1 h) does not generate toxic fumes. PA1 a) printed circuit boards formed from subtractive etching having excellent fine line electrical circuit quality (i.e., uniform line widths) via a high yielding process; PA1 b) printed circuit board intermediates utilizing thin photoresist layers, thereby fabricating printed circuit boards possessing a high density of circuits due to improved imaging resolution; PA1 c) printed circuit board intermediates utilizing thin layers of environmentally acceptable etch masks (i.e., elimination of the use of lead solder); PA1 d) a printed circuit board fabrication process of reduced complexity by removing the need for hole testing; PA1 e) a process for fabricating a laminate chip carrier that has reduced complexity by eliminating the need for a second photoresist application to selectively etch commoning bars; PA1 f) the fabrication of a laminate chip carrier that has improved wire bond yields and reliability due to elimination of the photoresist application and subsequent removal; and PA1 g) a process for fabricating PCB's having precision planar resistors.
The present invention further provides for processes of manufacture and designs of microelectronic packages, in particular printed circuit boards, having the following advantages: